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| Integrated Circuit Systems, Inc. AV9170 Clock Synchronizer and Multiplier General Description The AV9170 generates an output clock which is synchronized to a given continuous input clock with zero delay (1ns at 5V VDD). Using ICSs proprietary phase-locked loop (PLL) analog CMOS technology, the AV9170 is useful for regenerating clocks in high speed systems where skew is a major concern. By the use of the two select pins, multiples or divisions of the input clock can be generated with zero delay (see Tables 2 and 3). The standard versions produce two outputs, where CLK2 is always a divide by two version of CLK1. The AV9170 is also useful to recover poor duty cycle clocks. A 50 MHz signal with a 20/80% duty cycle, for example, can be regenerated to the 48/52% typical of the part. The AV9170 allows the user to control the PLL feedback, making it possible, with an additional 74F240 octal buffer (or other such device that offers controlled skew outputs), to synchronize up to 8 output clocks with zero delay compared to the input (see Figure 1). Application notes for the AV9170 are available. Please consult ICS. Features On-chip Phase-Locked Loop for clocks synchronization Synchronizes frequencies up to 107 MHz (output) @ 5.0V 1ns skew (max) between input & output clocks @ 5.0V Can recover poor duty cycle clocks CLK1 to CLK2 skew controlled to within 1ns @ 5.0V 3.0 - 5.5V supply range Low power CMOS technology Small 8-pin DIP or SOIC package On chip loop filter AV9170-01, -04 for output clocks 20-107 MHz @ 5.0V, 20 - 66.7 MHz @ 3.3V AV9170-02, -05 for output clocks 5-26.75 MHz @ 5.0V, 5 - 16.7 MHz @ 3.3V Block Diagram AV 9170 Rev E 9/24/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. AV9170 Pin Configuration 8-Pin DIP or SOIC Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME FBIN IN GND FS0 FS1 CLK1 VDD CLK TYPE Input Input -- Input Input Output -- Output DESCRIPTION FEEDBACK INPUT INPUT for reference clock GROUND FREQUENCY SELECT 0 FREQUENCY SELECT 1 CLOCK output 1 (See Tables 1, 2, 3, 4, 5 for values) Power Supply CLOCK output 2 (See Tables 1, 2, 3, 4, 5 for values) 2 AV9170 Using the AV9170 The AV9170 has the following characteristics: 1. Rising edges at IN and FBIN are lined up. Falling edges are not synchronized. 2. The relationship between the frequencies at FBIN and IN with CLK1 feedback is shown in Table 1 below. Eliminate High Speed Clock Routing Problems The AV9170 makes it possible to route lower speed clocks over long distances on the PC board and to place an AV9170 next to the device requiring a higher speed clock. The multiplied output can then be used to produce a phase locked, higher speed output clock. Functionality (Table 1:) FS1 0 0 1 1 FS0 0 1 0 1 fFBIN (-01, -02) fFBIN (-04, -05) 2 * f IN 3 * f IN 4 * f IN 5 * f IN f IN 6 * f IN 8 * f IN 10 * f IN Compensate for Propagation Delays Including an AV9170 in a timing loop allows the use of PALs, gate arrays, etc., with loose timing specifications. The AV9170 compensates for the delay through the PAL and synchronizes the output to the input reference clock. Operating Frequency Range The AV9170 is offered in versions optimized for operation in two frequency ranges. The -01 and -04 cover high frequencies, 20 to 100 MHz.* The -02 and -05 operate from 5 to 25 MHz.* The AV9170 can be supplied with custom multiplication factors and operating ranges. Consult ICS for details. 3. The frequency of CLK2 is half the CLK1 frequency. 4. The CLK1 frequency ranges are: VDD = 5V AV9170-01, -04 AV9170-02, -05 20 < fCLK1 < 5 < fCLK1 < 107 MHz* 26.75 MHz* VDD = 3.3V < 66.7 < 16.7 3.3V VDD Operation The AV9170 does operate at both 5.0V and 3.3V system conditions. Please note the Electrical Characteristic specifications at 3.3V include a limited output frequency (66.6 MHz max.) and a wider skew of FBIN to CLK1. For 3.3V5% (3.15V min.), this skew is -5.0 to 0 ns. At 3.3V10% (3.0V min.), the skew is widened to -8 ns to 0 ns and should be accounted for in system design. *At 3.3V, the maximum CLK1 frequency is 66.7 MHz for -01, -04 and 16.7 MHz for -02, -05. The AV9170 will only operate correctly within these frequency ranges. Figure 1: Application of AV9170 for Multiple Outputs 3 AV9170 Using CLK2 Feedback Connecting CLK2 to FBIN as shown in Figure 2 will cause all of the rising edges to be aligned (Figure 4). Using CLK1 Feedback With CLK1 connected to FBIN as shown in Figure 3, the input and CLK1 output will be aligned on the rising edge, but CLK2 can be either rising or falling (Figure 5). Consult ICS if the CLK1 frequency is desired to be higher than 107 MHz. Figure 2: Figure 3: For CLK2 frequencies 10 - 53.5 MHz* (-01) For CLK2 frequencies 2.5 - 13.37 MHz (-02) *Maximum 33.3 MHz @ 3.3V (-01), 8.33 MHz @ 3.3V (-02) For CLK1 frequencies 20 - 107 MHz (-01) For CLK1 frequencies 5 - 26.75 MHz (-02) Maximum 66.7 MHz @ 3.3V (-01), 16.7 MHz @ 3.3V (-02) Table 2: Functionality Table for AV9170-01, -02 with CLK2 Feedback FS1 0 0 1 1 FS0 0 1 0 1 CLK1 INx4 INx8 INx2 INx16 CLK2 INx2 INx4 IN INx8 Table 3: Functionality Table for AV9170-01, -02 with CLK1 Feedback FS1 0 0 1 1 FS0 0 1 0 1 CLK1 INx2 INx4 IN INx8 CLK2 IN INx2 IN/2 INx4 Figure 4: Input and Output Clock Waveforms with CLK2 Connected to FBIN Figure 5: Input and Output Clock Waveforms with CLK1 Connected to FBIN 4 AV9170 Using CLK2 Feedback Connecting CLK2 to FBIN as shown in Figure 6 will cause all of the rising edges to be aligned (Figure 8). Using CLK1 Feedback With CLK1 connected to FBIN as shown in Figure 7, the input and CLK1 output will be aligned on the rising edge, but CLK2 can be either rising or falling (Figure 9). Figure 6: Figure 7: For CLK2 frequencies 10 - 53 MHz* (-04) For CLK2 frequencies 2.5 - 13.37 MHz (-05) *Maximum 33.3 MHz @ 3.3V (-04), 8.33 MHz @ 3.3V (-05) For CLK1 frequencies 20 - 107 MHz (-04) For CLK1 frequencies 5 - 26.75 MHz (-05) Maximum 66.7 MHz @ 3.3V (-04), 16.7 MHz @ 3.3V (-05) Table 4: Functionality Table for AV9170-04, -05 with CLK2 Feedback FS1 0 0 1 1 FS0 0 1 0 1 CLK1 INx6 INx10 INx12 INx20 CLK2 INx3 INx5 INx6 INx10 Table 5: Functionality Table for AV9170-04, -05 with CLK1 Feedback FS1 0 0 1 1 FS0 0 1 0 1 CLK1 INx3 INx5 INx6 INx10 CLK2 INx1.5 INx2.5 INx3 INx5 Figure 8: Input and Output Clock Waveforms with CLK2 Connected to FBIN Figure 9: Input and Output Clock Waveforms with CLK1 Connected to FBIN 5 AV9170 Absolute Maximum Ratings VDD (referenced to GND) . . . . . . . . . . . . . . . . 7.0 V Operating Temperature under Bias . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C Voltage on I/O pins referenced to GND . . . . . GND 0.5 V to VDD + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 0.5 watts Stresses above those listed under Absolute Maximum Ratings above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 5V VDD = +5V 5%, TA = 0C to 70C, unless otherwise stated DC / CHARACTERISTICS PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Output High Voltage Output High Voltage Supply Current Supply Current SYMBOL VIL VIH IIL IIH *V O L *V O H 1 *V O H 2 *V O H 3 IDD1 IDD2 TEST CONDITIONS VDD = 5V VDD = 5V VIN = 0V VIN = VDD IOL = 8mA IOH = -1mA, VDD = 5.0V IOH = -4mA, VDD = 5.0V IOH = -8mA, Unloaded, 100 MHZ (-01, -04) Unloaded, 25 MHZ (-02, -05) MIN -- 2.0 -1.5 -- -- VDD -.4V VDD -.8V 2.4 -- -- TYP -- -- -5 -- -- -- -- -- 30 13 MAX 0.8 -- -- 5 0.4 -- -- -- 50 20 UNITS V V A A V V V V mA mA *Parameter guaranteed by design and characterization. Not 100% tested in production. Notes: 1. 2. 3. 4. It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application. All AC Specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V. Duty cycle measured at 1.4V. Skew measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal. 6 AV9170 Electrical Characteristics at 5V VDD = +5V 5%, TA = 0C to 70C, unless otherwise stated A/C CHARACTERISTICS PARAMETER Input Clock Rise Time Input Clock Fall Time Output Rise time, 0.8 to 2.0V Rise time, 20% to 80% VDD Output Fall time, 2.0 to 0.8V Fall time, 80% to 20% VDD Output Duty Cycle, AV9170-01 Output Duty Cycle, AV9170-02 Jitter, 1 sigma Jitter, absolute SYMBOL ICLKr* ICLKf* tr 1* tr 2* tf 1* tf 2* dt 1* dt 2* T1s* TEST CONDITIONS MIN -- -- -- -- -- -- 40 45 -- -500 TYP -- -- 0.6 1.2 0.4 0.9 48/52 49/51 125 -- MAX 10 10 2 3 2 2 60 55 300 500 UNITS ns ns ns ns ns ns % % ps ps 15pF load. 15pF load. 15pF load. 15pF load. 15pF load. Note 2, 3 15pF load. Note 2, 3 Jitter, absolute Input Frequency Input Frequency Output Frequency CLK1 Output Frequency CLK1 FBIN to IN skew FBIN to IN skew CLK1 to CLK2 skew For CLK1 > 10 MHz (-01, -04) Ta b s 1 * For CLK1 > 2.5 MHz (-02, -05) For CLK1 < 10 MHz (-01, -04) Ta b s 2 * For CLK1 < 2.5 MHz (-02, -05) fi1 Note 1, AV9170-01, -04 fi2 AV9170-02, -05 fo1 AV9170-01, -04 AV9170-02, -05 fo2 Note 2, 4; 15pF load T s k ew 1 * Input rise time < 5ns Note 2, 4; 15pF load T s k ew 2 * Input rise time < 10ns T s k ew 3 * Note 2, 4 -- 8 2 20 5 -1 -2 -1 -- -- -- -- -- -0.3 -0.3 0.4 2 107 26.75 107 26.75 1 2 1 % MHz MHz MHz MHz ns ns ns *Parameter guaranteed by design and characterization. Not 100% tested in production. Notes: 1. 2. 3. 4. It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application. All AC Specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V. Duty cycle measured at 1.4V. Skew measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal. 7 AV9170 Electrical Characteristics at 3.3V VDD = +3.3V 5%, TA = 0C to 70C, unless otherwise stated DC / CHARACTERISTICS PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Output High Voltage Output High Voltage Supply Current Supply Current SYMBOL VIL VIH IIL IIH *V O L *V O H 1 *V O H 2 *V O H 3 IDD1 IDD2 TEST CONDITIONS VDD = 3.3V VDD = 3.3V VIN = 0V VIN = VDD IOL = 6mA IOH = -1mA, VDD = 3.3V IOH = -3mA, VDD = 3.3V IOH = -6mA, Unloaded, 66.7 MHZ (-01, -04) Unloaded, 16.7 MHZ (-02, -05) MIN -- 0.7 V D D -7 -- -- VDD -.4V VDD -.8V 2.4 -- -- TYP -- -- -4 -- -- -- -- -- 17 7 MAX 0.2 V D D -- -- 5 0.4 -- -- -- 30 15 UNITS V V A A V V V V mA mA *Parameter guaranteed by design and characterization. Not 100% tested in production. 1. 2. 3. 4. Notes: It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application. All AC Specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V. Duty cycle measured at 1.4V. Skew measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal. 8 AV9170 Electrical Characteristics at 3.3V VDD = +3.3V 5%, TA = 0C to 70C, unless otherwise stated A/C CHARACTERISTICS PARAMETER Input Clock Rise Time Input Clock Fall Time Output Rise time, 0.8 to 2.0V Rise time, 20% to 80% VDD Output Fall time, 2.0 to 0.8V Fall time, 80% to 20% VDD Output Duty Cycle, AV9170-01, -04 Output Duty Cycle, AV9170-02, -05 Jitter, 1 sigma Jitter, absolute SYMBOL ICLKr* ICLKf* tr 1* tr 2* tf 1* tf 2* dt 1* dt 2* T1s* TEST CONDITIONS MIN -- -- -- -- -- -- 40 45 -- -500 TYP -- -- 1.1 1.8 0.8 1.2 52 51 150 -- MAX 10 10 2 4 2 3 60 55 300 500 UNITS ns ns ns ns ns ns % % ps ps 15pF load. 15pF load. 15pF load. 15pF load. 15pF load. Note 2, 3 15pF load. Note 2, 3 Jitter, absolute Input Frequency Input Frequency Output Frequency CLK1 Output Frequency CLK1 FBIN to IN skew FBIN to IN skew CLK1 to CLK2 skew For CLK1 > 10 MHz (-01, -04) Ta b s 1 * For CLK1 > 2.5 MHz (-02, -05) For CLK1 < 10 MHz (-01, -04) Ta b s 2 * For CLK1 < 2.5 MHz (-02, -05) fi1 AV9170-01, -04 fi2 AV9170-02, -05 fo1 AV9170-01, -04 AV9170-02, -05 fo2 Note 2, 4; 15pF load T s k ew 1 * 3.0 VDD 3.7 No 4 15 F l T s k ew 2 * 3.0te 2, D;D p3.7oad V T s k ew 3 * Note 2, 4; 15pF load -2 7 2 20 5 -8.0 -5.0 -2.0 -- -- -- -- -- -2.0 -2.0 -0.9 2 66.7 16.7 66.7 16.7 0 0 0 % MHz MHz MHz MHz ns ns ns *Parameter guaranteed by design and characterization. Not 100% tested in production. Notes: 1. 2. 3. 4. It may be possible to operate the AV9170 outside of these ranges. Consult ICS for your specific application. All AC Specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V. Duty cycle measured at 1.4V. Skew measured at 1.4V on rising edges. Positive sign indicates the first signal precedes the second signal. 9 AV9170 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. Connections to VDD: 10 AV9170 8-Pin DIP PACKAGE 8-Pin SOIC PACKAGE Ordering Information AV9170-xxCN8 (8 Lead Plastic DIP [300 mils] ) AV9170-xxCS8 (8 Lead SOIC [150 mils] ) Example: ICS XXXX - PPP M X#W Lead Count & Package Width Lead Count = 1, 2 or 3 digits W = 0.3" SOIC or 0.6" DIP; None = Standard Width Package Type N = DIP (Plastic) S = SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device; AV = ICS (West Coast) For the SOIC package, the AV9170-01 is marked AV70-1 and the AV9170-02 is marked AV70-2. 11 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. |
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